Integrated circuit elements and the metallic interconnecting conductors thereon can be patterned on a wafer entirely by means of direct writing electron beam lithography (EBL). However, this fabrication technique requires excessive beam writing time of complex and expensive EBL machines and the complex circuit and conductor patterns so lithographed with many different spacings and widths of lithographed features requires complex correction of the computer-stored pattern to correct for proximity effects. Proximity effects are the widening of the lithographed features caused by forward and backscattering of the electron beam as it penetrates the electron resist material which covers the wafer. The magnitude of the proximity effect and hence the correction factor required is a function, among other things, of the widths of the features being lithographed.
The use of photolithography to imprint patterns on a chip or wafer by means of a patterned mask has been extensively used in the past for the fabrication of VHSIC/VLSI circuits. In fact, for historic and practical reasons, such as noted above, the use of patterned masks for IC fabrication is far-and-away the most common technique used today in IC fabrication.
U.S. Pat. No. 4,610,948, issued Sept. 9, 1986 to the present inventor, disclosed a hybrid technique which overcame some of the noted disadvantages associated with the direct writing EBL technique, as well as those theretofore encountered using patterned masks. The method of the patent achieves high accuracy, high density lithographing of complex integrated circuits (VHSIC/VLSI) in a relatively economical and simple manner. Unfortunately, this hybrid technique, which relies on a combination of direct writing e-beam lithography (EBL) with the use of patterned masks, has "throughput" limitations. While this technique or process is more efficient (i.e., faster) than the direct writing EBL approach, its throughput is less than the straight-forward use of patterned masks for IC fabrication.